Difference between revisions of "DataflowBibliography"

Revision as of 02:10, 9 March 2006

Conference Papers

• Arvind, Robert A. lannucci "A Critique of Multiprocessing von Neumann Style" In Proceedings of the 10th annual international symposium on Computer architecture, 1983. http://portal.acm.org/citation.cfm?id=801684

Lays out two "fundamental" requirements for good parallel processing: The ability to tolerate long-latency memory operations and fast synchronization. they critique a range of multiprocessors and describe their own. I think it's the TTDA.
swanson 16:46, 8 March 2006 (PST)

• Culler, David E., Klaus Erik Schauser, Thorsten von Eicken "Two Fundamental Limits on Dataflow Multiprocessing", Proceedings of the IFIP Working Group 10.3 (Concurrent Systems) Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, Jan. 1993. http://www.eecs.berkeley.edu/Pubs/TechRpts/1992/CSD-92-716.pdf

This is the "dataflow is dead" paper. There are two arguments. First, you can't keep enough threads close to the processor to cover the latency of communication, because the top of the memory hierarchy is small. Second, even if you have smarter local scheduler that does its best to exploit locality (via TAM), performance is still not good enough. They argue that you need a global scheduling strategy instead of the local strategy that the dataflow firing rule defines. If you apply their analytic model to WaveScalar, it shows that performance is fine as long as we can localize communication pretty well and we can fit the working set of instructions into the array.
swanson 16:46, 8 March 2006 (PST)

• Dennis, Jack B. and David P. Misunas. "A preliminary architecture for a basic dataflow processor." In the Proceedings of the 2nd Annual Symposium on Computer Architecture (ISCA), 1975. http://doi.acm.org/10.1145/642089.642111

Description of static dataflow and an architecture for executing programs composed of static dataflow graphs. This is a very early paper on the topic of dataflow architectures, if not the earliest. The first few pages provide a reasonable introduction to the fundamentals of dataflow computation, though they are limited (I believe) to static dataflow models. The architecture described foreshadows that of many future dataflow machines, and the instruction caching problem that became the matching table overflow problem of later machines is discussed (or at least mentioned).
Schwerin 13:25, 5 January 2006 (PST)

• Arvind and Kathail. "A multiple processor data flow machine that supports generalized procedures." In the Proceedings of the 8th Annual Symposium on Computer Architecture (ISCA), 1981. ACM lists no DOI for this object, but it's in the digital library.

I believe this paper describes the architecture of the MIT tagged-token dataflow machine.
Schwerin 14:37, 9 January 2006 (PST)

• Grafe, V.G., G.S. Davidson, J.E. Hoch, and V.P. Holmes. "The Epsilon Dataflow Processor." In the Proceedings of the 16th Annual International Symposium on Computer Architecture (ISCA), 1989. http://doi.acm.org/10.1145/74925.74930

• Nikhil, R.S. "Can dataflow subsume von Neumann computing?" In the Proceedings of the 16th Annual International Symposium on Computer Architecture (ISCA), 1989. http://doi.acm.org/10.1145/74925.74955

This paper describes the P-RISC architecture, which adds dataflow features to RISC-style multiprocessors. The features come from the addition of fine grain threading and synchronization operations at the ISA level.
Schwerin 14:19, 9 January 2006 (PST)

• T. Shimada, K. Hiraki, K. Nishida, S. Sekiguchi "Evaluation of a Prototype Data Flow Processor of the SIGMA-1 for Scientific Computations" Proceedings of the 13th annual international symposium on Computer architecture, 1983. http://doi.acm.org/10.1145/17407.17383

Describes the Sigma-1, an early dataflow machine from Japan. They have a single processing element from a 128 element system. The proposed system uses a hierarchical network to allow the PEs to communicate. They evaluate its performance on a bunch of small loops and compare it to a single von Neumann core. They measure the extra loop and control overhead that dataflow requires and add some special instructions to reduce it.
swanson 17:27, 8 March 2006 (PST)

• Sakai, S., Y. Yamaguchi, K. Hiraki, Y. Kodama and T. Yuba. "An architecture of a dataflow single chip processor." In the Proceedings of the 16th Annual International Symposium on Computer Architecture (ISCA), 1989. http://doi.acm.org/10.1145/74925.74931

Description of the EM-4, a follow-on to the Sigma-1. EM-4 was to be a first dataflow multiprocessor in which every processing node occupied no more than a single chip. Describes a strongly connected arc model, which is broadly similar to the Monsoon frame model and its ilk. Another similarity to Monsoon is a frame-based matching scheme implemented with normal memories. Discusses shortcomings of prior dataflow machines. Attempts to address these in the new architecture.
Schwerin 13:45, 5 January 2006 (PST)

• Papadopoulos, Gregory M., and Kenneth R. Traub. "Multithreading: a revisionist view of dataflow architectures." In the Proceedings of the 18th Annual International Symposium on Computer Architecture (ISCA), 1991. http://doi.acm.org/10.1145/115952.115986

This paper looks at the Monsoon dataflow architecture as a multithreaded computer with fine-grain threads.
Schwerin 14:19, 9 January 2006 (PST)

Refereed Journal Papers

• Arvind and Nikhil, V.C. "Executing a program on the MIT tagged-token dataflow architecture." In IEEE Transactions on Computers, March, 1990. http://doi.ieeecomputersociety.org/10.1109/12.48862